• BI-HR/23-24-009 - Visoko zmogljivo računanje na RISC-V vektorskih procesorjih
The Client : ( BI-HR/23-24-009 )
Project type: Bilateral projects
Project duration: 2023 - 2026
  • Description

Exascale computation systems must meet performance, cost, and energy efficiency challenges simultaneously. Nowadays, computing platforms built around the RISC-V processor are rapidly gaining acceptance as an open-sourced alternative to commercial processors. Compared with existing RISC architectures such as ARM or MIPS, RISC-V allows custom extensions of instruction set architecture to support the design needs. The open-source nature of RISC-V architecture led to its broad acceptance and widespread usage from IoT applications to HPC. Leading companies such as Intel, Google, Huawei and many more actively contribute to the RISC-V development. Inspired by the RISC-V success, the European Processor Initiative (EPI) has been working on providing the independence of the European Union in high-performance computing (HPC). EPI's goal is to develop a custom RISC-V vector processor, called the European Processor Accelerator Chip (EPAC), designed for high efficiency and high throughput computation. The EPAC should be energy-efficient, extreme-scale, suitable for HPC and embedded applications, and extensible (easy to add on-chip and off-chip components).